ARM Embedded

Systems
Organization of Syllabus
• Chapter 1 introduces a simple embedded system based on the ARM processor.
• Chapter 2 digs more deeply into the hardware, focusing on the ARM processor core and
presents an overview of the ARM cores currently in the marketplace.
• The ARM and Thumb instruction sets are the focus of Chapters 3 and 4, respectively.
• Chapters 5 demonstrate how to write efficient code with lots of example. Chapter 5 teaches
proven techniques and rules for writing C code that will compile efficiently on the ARM
architecture.
• Chapter 9 covers the theory and practice of handling exceptions and interrupts on the ARM
processor through a set of detailed examples.
• Firmware, an important part of any embedded system, is described in Chapter 10 by means of
a simple firmware package designed by authors of text book, called Sandstone.
• Chapter 11 demonstrates the implementation of embedded operating systems through an
example operating system we designed, called Simple Little Operating System.
• Chapter 12 examines the various cache technologies that surround the ARM cores,
demonstrating routines for controlling the cache on specific cache-enabled ARM processors.
Module-1
• Introduction • Embedded system Software
• RISC design philosophy • Initialization (Boot) code
• Embedded system Hardware • Operating System
• AMBA bus protocol • Applications
• Memory
• Peripherals
Nomenclature
RISC design philosophy v/s ARM design philosophy
• RISC design philosophy is aimed at delivering simple but powerful instructions that execute within a
single cycle at a high clock speed.
• Main idea behind is to make hardware simpler by using an instruction set composed of a few basic
steps for loading, evaluating, and storing operations, intelligence is provided in software rather
than hardware.

• RISC philosophy is implemented with 4 major design rules,

i. Instructions: RISC class provide simple operations that can each execute in a single
cycle. The compiler or programmer synthesizes complicated operations of fixed
length allowing pipelining.
ii. Pipelines: The processing of instructions is broken down into smaller units that can be
executed in parallel by pipelines. Ideally the pipeline advances by one step on each
cycle for maximum throughput.
iii. Registers: RISC machines have a large general-purpose register set. Any register can
contain either data or an address. Registers act as the fast local memory store
iv. Load store architecture: The processor operates on data held in registers. Separate
load and store instructions transfer data between the register bank and
external memory.
CISC v/s RISC
ARM Design Philosophy
• Physical features driving ARM design
i. Portable embedded system – depend on battery- mobile, PDA
ii. Limited memory – High code density
iii. ARM has incorporated hardware debug technology within the processor so that
software engineers can view what is happening while the processor is executing code.
iv. single-chip solution, the smaller the area used by the embedded processor, the more
available space for specialized peripherals.
v. The ARM core is not a pure RISC architecture because of the constraints of its primary
application—the embedded system.
In some sense, the strength of the ARM core is that it does not take the RISC
concept too far. In today’s systems the key is not raw processor speed but total effective
system performance and power consumption.
Instruction Set for Embedded Systems
• Variable cycle execution for certain instructions—Not every ARM instruction executes in a single
cycle.
Ex: load-store-multiple instructions vary in the number of execution cycles depending upon the number of
registers being transferred.
Code density is also improved since multiple register transfers are common operations at the start and end of
functions.
• Inline barrel shifter leading to more complex instructions—The inline barrel shifter is a
hardware component that preprocesses one of the input registers before it is used by an
instruction. This expands the capability of many instructions to improve core performance and
code density.
• Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second 16-bit
instruction set called Thumb that permits the ARM core to execute either 16- or 32-bit
instructions. The 16-bit instructions improve code density by about 30% over 32-bit fixed-length
instructions.
• Conditional execution—An instruction is only executed when a specific condition has been
satisfied. This feature improves performance and code density by reducing branch instructions.
• Enhanced instructions—The enhanced digital signal processor (DSP) instructions were added to
the standard ARM instruction set to support fast 16×16-bit multiplier operations and saturation.
These instructions allow a faster-performing ARM processor in some cases to replace the
traditional combinations of a processor plus a DSP.
Embedded System Hardware

Emb system controls

Sensor in production pipeline Real time control system used in NASA space mission

• Devices use a combination of software and hardware components

• Device is designed for efficiency, future extension and expansion.
ARM based embedded device
Embedded System
• Device can be divided into four main hardware components,
i. The ARM processor controls the embedded device. Different versions of
the ARM processor are available to suit the desired operating
characteristics. An ARM processor comprises a core (the execution
engine that processes instructions and manipulates data) plus the
surrounding components that interface it with a bus. These components
can include memory management and caches.
ii. Controllers coordinate important functional blocks of the system. Two
commonly found controllers are interrupt and memory controllers.
iii. The peripherals provide all the input-output capability external to the chip
and are responsible for the uniqueness of the embedded device.
iv. A bus is used to communicate between different parts of the device.
ARM bus technology
• PCI in X86 PCs [Peripheral Component Interface]
• Connects video cards and hard disk controllers to the x86 processor bus.
• PCI is external/ off-chip technology
• Embedded devices use an on-chip bus that is internal to the chip and that allows
different peripheral devices to be interconnected with an ARM core.
• Two different classes of devices attached to the bus -
1. The ARM processor core is a bus master—a logical device capable of initiating a data transfer
with another device across the same bus.
2. Peripherals tend to be bus slaves—logical devices capable only of responding to a transfer
request from a bus master device.
• A bus has two architecture levels -
1. The first is a physical level that covers the electrical characteristics and bus width (16, 32, or
64 bits).
2. The second level deals with protocol—the logical rules that govern the communication
between the processor and a peripheral.
AMBA Bus Protocol
• Acronym for Advanced Microcontroller Bus Architecture (AMBA).
• Introduced in 1996.
• Widely adopted as the on-chip bus architecture used for ARM processors.
• The first AMBA buses introduced were
I. ARM System Bus (ASB)
II. ARM Peripheral Bus (APB)
III. Later ARM introduced another bus design, called the ARM High Performance Bus (AHB).
• Peripheral designers can reuse the same design on multiple projects. Because there are a large
number of peripherals developed with an AMBA interface, hardware designers have a wide choice
of tested and proven peripherals for use in a device.
• plug-and-play interface for hardware developers improves availability and time to market.
• AHB provides higher data throughput than ASB because it is based on a centralized multiplexed
bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at
higher clock speeds.
• ARM has introduced two variations on the AHB bus:
I. Multi-layer AHB
II. AHB-Lite.
Memory
• An embedded system has to have some form of memory to store and
execute code.
• Compare price, performance, and power consumption when deciding upon
specific memory characteristics, such as hierarchy, width, and type.
• To maintain a desired bandwidth, if memory runs at a faster rate then its
power consumption will also increase.
Memory Hierarchy
• Memory trade-offs:
• the fastest memory cache is physically located nearer the ARM
processor core and the slowest secondary memory is set further
away.
• Generally the closer memory is to the processor core, the more it
costs and the smaller its capacity.
• The cache is placed between main memory and the core. It is used
to speed up data transfer between the processor and main memory.
A cache provides an overall increase in performance but with a loss
of predictable execution time.
• The main memory/primary/direct CPU access is large—around 256
KB to 256 MB (or even greater), depending on the application—and
is generally stored in separate chips.
• Load and store instructions access the main memory unless the
values have been stored in the cache for fast access.
• Secondary/auxillary storage is the largest and slowest form of
memory.
Memory Width
• The memory width is the number of bits the memory returns on each
access—typically 8, 16, 32, or 64 bits. The memory width has a direct
effect on the overall performance and cost ratio.
• If you have an uncached system using 32-bit ARM instructions and 16-bit-
wide memory chips, then the processor will have to make two memory
fetches per instruction.
• Each fetch requires two 16-bit loads.
• In contrast, if the core executes 16-bit Thumb instructions, it will achieve
better performance with a 16-bit memory.
• The higher performance is a result of the core making only a single fetch to
memory to load an instruction. Hence, using Thumb instructions with 16-
bit-wide memory devices provides both improved performance and
reduced cost.
Theoretical cycle times on an ARM processor
using different memory width devices.
Memory Types
 Memory Types
• Read-only memory (ROM) is
• The least flexible of all memory types
• it contains an image that is permanently set at production time and cannot be
reprogrammed.
• ROMs are used in high-volume devices that require no updates or corrections.
• Many devices also use a ROM to hold boot code.
• Flash ROM can be
• written to as well as read, but it is slow to write so you shouldn’t use it for
holding dynamic data.
• Its main use is for holding the device firmware or storing long term data that
needs to be preserved after power is off.
• The erasing and writing of flash ROM are completely software controlled with no
additional hardware circuity required, which reduces the manufacturing costs.
• Flash ROM has become the most popular of the read-only memory types and is
currently being used as an alternative for mass or secondary storage.
 Memory Types
• Dynamic random access memory(DRAM) is the
• most commonly used RAM for devices. It has the lowest cost per
megabyte compared with other types of RAM.
• DRAM is dynamic—it needs to have its storage cells refreshed and
given a new electronic charge every few milliseconds, so you need to
set up a DRAM controller before using the memory.
• Static random access memory (SRAM) is faster than the more
traditional DRAM, but requires more silicon area.
• SRAM is static. So, the RAM does not require refreshing.
• The access time for SRAM is considerably shorter than the equivalent
DRAM .
• because SRAM does not require a pause between data accesses.
• Because of its higher cost, it is used mostly for smaller high-speed
tasks, such as fast memory and caches.
Memory types
• Synchronous dynamic random access memory (SDRAM) is one of many
subcategories of DRAM.
• It can run at much higher clock speeds than conventional memory.
• SDRAM synchronizes itself with the processor bus because it is clocked.
Internally the data is fetched from memory cells, pipelined, and finally
brought out on the bus in a burst.
• The old-style DRAM is asynchronous, so does not burst as efficiently as
SDRAM.
Peripherals
• Embedded systems that interact with the outside world need some form of
peripheral device.
• A peripheral device performs input and output functions for the chip by
connecting to other devices or sensors that are off-chip.
• Peripherals range from a simple serial communication device to a more complex
802.11 wireless device.
• All ARM peripherals are memory mapped—the programming interface is a set of
memory-addressed registers. The address of these registers is an offset from a
specific peripheral base address.
• Controllers are specialized peripherals that implement higher levels of
functionality within an embedded system. Two important types of controllers are
I. Memory controllers
II. Interrupt controllers.
Memory Controllers
• Memory controllers connect different types of memory to the processor
bus.
• On power-up a memory controller is configured in hardware to allow
certain memory devices to be active.
• These memory devices allow the initialization code to be executed. Some
memory devices must be set up by software.
• Ex: when using DRAM, you first have to set up the memory timings and
refresh rate before it can be accessed.
Interrupt controllers
Interrupt controllers
Interrupt controllers
Interrupt controllers
• When a peripherals requires attention, it raises an interrupt to
the processor.
• An interrupt controller provides a programmable governing
policy that allows software to determine which peripheral can
interrupt the processor at any specific time by setting the
appropriate bits in the interrupt controller registers.
• There are two types of interrupt controller available for the ARM
processor:
• Standard interrupt controller
• Vector interrupt controller (VIC).
Interrupt controllers : Standard interrupt controller
• SIC sends an interrupt signal to the processor core when an external
device requests servicing.
• It can be programmed to ignore or mask an individual device or set of
devices.
• The interrupt handler determines which device requires servicing by
reading a device bitmap register in the interrupt controller.
Interrupt controllers : Vector interrupt controller
• The VIC is more powerful than the standard interrupt controller because it
prioritizes interrupts and simplifies the determination of which device
caused the interrupt.
• After associating a priority and a handler address with each interrupt, the
VIC only asserts an interrupt signal to the core if the priority of a new
interrupt is higher than the currently executing interrupt handler.
• Depending on its type, the VIC will either call the standard interrupt
exception handler, which can load the address of the handler for the
device from the VIC, or cause the core to jump to the handler for the
device directly.
What happens when you turn your system ON?
Embedded system software
• An embedded system needs software to drive it.
• Figure below shows four typical software components required to control an embedded
device. Each software component in the stack uses a higher level of abstraction to
separate the code from the hardware device.
Embedded system software
• The initialization code is the first code executed on the board and is specific to a
particular target or group of targets.
• It sets up the minimum parts of the board before handing control over to the operating
system.
• The operating system provides an infrastructure to control applications and manage
hardware system resources.
• Many embedded systems do not require a full operating system but merely a simple task
scheduler that is either event or poll driven.
• Device drivers are the third component . They provide a consistent software interface to
the peripherals on the hardware device.
• an application performs one of the tasks required for a device.
• Ex: a mobile phone might have a diary application. There may be multiple applications
running on the same device, controlled by the operating system.
Initialization (Boot) Code Initialization (Boot) Code
• Initialization code (or boot code) takes the processor from the reset state to a
state where the operating system can run.
• The initialization code handles a number of administrative tasks prior to
handing control over to an operating system image.
• Initialization has three tasks:
• Initial hardware configuration
• Diagnostics
• Booting.
• Initial hardware configuration involves setting up the target platform so it can
boot an image.
• Diagnostics are often embedded in the initialization code. Diagnostic code
tests the system by exercising the hardware target to check if the target is in
working order. It also tracks down standard system-related issues.
• The primary purpose of diagnostic code is fault identification and isolation.
• Booting an image is the final phase, but first you must load the image. Loading
an image involves anything from copying an entire program including code
and data into RAM, to just copying a data area containing volatile variables
into RAM.
Initializing or organizing memory
• Many operating systems expect a few know memory
layout before they can start.
• Figure shows memory before and after reorganization.
• It is common for ARM-based embedded systems to
provide for memory remapping because it allows the
system to start the initialization code from ROM at
power-up.
• The initialization code then remaps the memory map to
place RAM at address 0x00000000—an important step
because then the exception vector table can be in
RAM and thus can be reprogrammed.
Operating System
• The initialization process prepares the hardware for an
operating system to take control.
• An operating system organizes the system resources:
i. the peripherals,
ii. memory, and
iii. processing time.
• With an operating system controlling these resources, they
can be efficiently used by different applications running
within the operating system environment.
• ARM processors support over 50 operating systems.
• Operating systems can be divided into two main categories:
I. Real-time operating systems (RTOSs)
II. Platform operating systems.
Operating System
• RTOSs provide guaranteed response times to events.
• Different operating systems have different amounts of control over the
system response time.
• A hard real-time application requires a guaranteed response to work at
all.
• In contrast, a soft real-time application requires a good response time,
but the performance degrades more gracefully if the response time
overruns. Systems running an RTOS generally do not have secondary
storage.
• Platform operating systems require a memory management unit to
manage large, non real-time applications and tend to have secondary
storage. Ex: The Linux operating system.
• These two categories of operating system are not mutually exclusive:
there are operating systems that use an ARM core with a memory
management unit and have real-time characteristics. ARM has developed
a set of processor cores that specifically target each category.
Applications
• The operating system schedules application (code dedicated to handling a particular
task).
• An embedded system can have one active application or several applications running
simultaneously.
• ARM processors are found in numerous market segments,
i. networking,
ii. automotive,
iii. mobile
iv. consumer devices, mass storage, and imaging.
• Ex: the ARM processor is found in networking applications like home gateways, DSL
modems for high-speed Internet communication, and 802.11 wireless communication.
• The mobile device segment is the largest application area for ARM processors
because of mobile phones.
• ARM processors are also found in mass storage devices such as hard drives and
imaging products such as inkjet printers—applications that are cost sensitive and high
volume.
ARM Processor fundamentals
• Focus on the actual processor  overview of the processor core  describe how data
moves between its different parts.
• Describe the programmer’s model from a software developer’s view of the ARM
processor, which will show the functions of the processor core and how different parts
interact.
• The core extensions that form an ARM processor.
• Core extensions speed up and organize main memory as well as extend the instruction
set.
• Naming conventions used to identify ARM cores.
• chronological changes to the ARM instruction set architecture.
 Data flow

• A programmer can think of an ARM

core as functional units connected
by data buses.
• The arrows represent the flow of
data,
• The lines represent the buses,
• The boxes represent either an
operation unit or a storage area.
• The figure shows not only the flow
of data but also the abstract
components that make up an ARM
core.
Data flow
• Data enters the processor core through the Data bus. The data may be an instruction
to execute or a data item.
• Von Neumann implementation of the ARM— data items and instructions share the
same bus. In contrast, Harvard implementations of the ARM use two different buses.
• The instruction decoder translates instructions before they are executed.
• The ARM processor, like all RISC processors, uses a load-store architecture. This
means it has two instruction types for transferring data in and out of the processor:
load instructions copy data from memory to registers in the core, and conversely the
store instructions copy data from registers to memory.
• Data items are placed in the register file—a storage bank made up of 32-bit registers.
Since the ARM core is a 32-bit processor, most instructions treat the registers as
holding signed or unsigned 32-bit values. The sign extend hardware converts signed 8-
bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a
register.
• ARM instructions typically have two source registers, Rn and Rm,
• and a single result or destination register, Rd.
• Source operands are read from the register file using the internal buses A and B,
respectively.
Data flow
• The ALU (arithmetic logic unit) & MAC (multiply-accumulate unit) takes the register
values Rn and Rm from the A and B buses and computes a result.
• Data processing instructions write the result in Rd directly to the register file.
• Load and store instructions use the ALU to generate an address to be held in the
address register and broadcast on the Address bus.
• One important feature of the ARM is that register Rm alternatively can be
preprocessed in the barrel shifter before it enters the ALU.
• Together the barrel shifter and ALU can calculate a wide range of expressions and
addresses.
• The result in Rd is written back to the register file using the Result bus.
• For load and store instructions the incrementer updates the address register before
the core reads or writes the next register value from or to the next sequential
memory location.
• The processor continues executing instructions until an exception or interrupt
changes the normal execution flow.
 Registers
• General-purpose registers hold either data or an address. They
are identified with the letter r prefixed to the register number.
• Ex: register 4 is given the label r4.
• There are up to 18 active registers:
• 16 data registers and 2 processor status registers.
• data registers are visible to the programmer as r0 to r15.
• Register r13 is traditionally used as the stack pointer (sp) and
stores the head of the stack in the current processor mode.
• Register r14 is called the link register (lr) and is where the
core puts the return address whenever it calls a subroutine.
• Register r15 is the program counter (pc) and contains the
address of the next instruction to be fetched by the processor.
CPSR
• ARM core uses the CPSR to monitor and control internal
operations.
• The CPSR is divided into four fields, each 8 bits wide:
• flags,
• status,
• extension,
• and control.
• The control field contains the processor mode, state,
and interrupt mask bits.
• The flags field contains the condition flags.
CPSR
Processor Modes
• The processor mode determines which registers are active and the access rights to the cpsr register
itself.
• Each processor mode is either privileged or nonprivileged.
• A privileged mode allows full read-write access to the cpsr.
• Conversely, a nonprivileged mode only allows read access to the control field in the cpsr but still
allows read-write access to the condition flags.
• There are seven processor modes in total:
• six privileged modes
I. abort,
II. fast interrupt request,
III. interrupt request,
IV. supervisor,
V. system
VI. undefined
• one nonprivileged mode
I. user.
Processor modes
1. The processor enters abort mode when there is a failed
attempt to access memory.
2. Fast interrupt request and interrupt request modes correspond
to the two interrupt levels available on the ARM processor.
3. Supervisor mode is the mode that the processor is in after
reset and is generally the mode that an operating system
kernel operates in.
4. System mode is a special version of user mode that allows full
read-write access to the cpsr.
5. Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation.
6. User mode is used for programs and applications.
Banked registers
Changing mode on exception
• when the processor is in the interrupt
request mode, the instructions you execute
still access registers named r13 and r14.
• However, these registers are the banked
registers r13_irq and r14_irq.
• The user mode registers r13_usr and r14_usr
are not affected by the instruction
referencing these registers.
Modes and mode bit fields in CPSR [0:4]
State and Instruction Sets
• The state of the core determines which instruction set is being
executed.
• There are three instruction sets:
1. ARM,
2. Thumb, and
3. Jazelle.
• The ARM instruction set is only active when the processor is in
ARM state. Similarly the Thumb instruction set is only active
when the processor is in Thumb state.
• Once in Thumb state the processor is executing purely Thumb
16-bit instructions. You cannot intermingle sequential ARM,
Thumb, and Jazelle instructions.
State and Instruction Sets
• The Jazelle J and Thumb T bits in the CPSR reflect the state of the
processor.
• When both J and T bits are 0, the processor is in ARM state and
executes ARM instructions.
• This is the case when power is applied to the processor.
• When the T bit is 1, then the processor is in Thumb state. To
change states the core executes a specialized branch instruction.
• The ARM designers introduced a third instruction set called
Jazelle. Jazelle executes 8-bit instructions and is a hybrid mix of
software and hardware designed to speed up the execution of
Java bytecodes.
Condition Flags

Q flag is set to 1 when saturation has occurred in saturating arithmetic instructions, or when overflow
has occurred in certain multiply instructions.

"Signed overflow" means that you tried to store a value that's outside the range of values that the
type can represent, and the result of that operation is undefined
Condition Flags
• Condition flags are updated by comparisons and the
result of ALU operations that specify the S instruction
suffix.
• For ex:
if a SUBS subtract instruction results in a register value
of zero, then the Z flag in the CPSR is set
Interrupt Masks
• Interrupt masks are used to stop specific interrupt requests from
interrupting the processor.
• There are two interrupt request levels available on the ARM processor
core
A. interrupt request (IRQ) and
B. fast interrupt request (FIQ).
• The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which control
the masking of IRQ and FIQ, respectively.
• The I bit masks IRQ when set to binary 1, and similarly the F bit masks
FIQ when set to binary 1.
Pipeline
• A pipeline is the mechanism a RISC processor uses to
execute instructions.
• Using a pipeline speeds up execution by fetching the
next instruction while other instructions are being
decoded and executed.
a) Fetch loads an instruction from memory.
b) Decode identifies the instruction to be executed.
c) Execute processes the instruction and writes the
result back to a register.
Pipeline
Pipeline
• The three instructions are placed into the pipeline sequentially.
• In the first cycle the core fetches the ADD instruction from
memory.
• In the second cycle the core fetches the SUB instruction and
decodes the ADD instruction.
• In the third cycle, both the SUB and ADD instructions are
moved along the pipeline. The ADD instruction is executed, the
SUB instruction is decoded, and the CMP instruction is fetched.
• This procedure is called filling the pipeline. The pipeline
allows the core to execute an instruction every cycle.
• As the pipeline length increases, the amount of work done at
each stage is reduced, which allows the processor to attain a
higher operating frequency.
Pipeline