VHDL- gate level modelling

Verilog Hardware Description
Language
Define Modules,Ports, Gate level Modelling
-Prof.Vandana Pagar
Assistant professor

Learning Objectives:
• Identify the components of aVerilog module
definition, such as module names, port lists,
parameters, variable declarations, dataflow
statements, behavioral statements,
instantiation of other modules, and tasks or
functions.
 Understand how to define the port list for a
module and declare it inVerilog.
 Describe the port connection rules in a
module instantiation.
 Understand how to connect ports to
external signals, by ordered list, and by
name.

Learning Objectives:
 Identify logic gate primitives provided in
Verilog.
 Understand instantiation of gates, gate symbols
and truth tables for and/or and buf/not type
gates.
 Understand how to construct aVerilog
description from the logic diagram of the
circuit.
 Describe rise, fall, and turn-off delays in the
gate-level design.
 Explain min, max, and type delays in the gate-
level design.

Modules and Ports
 A module inVerilog consists of distinct parts, as shown
in Figure.

Modules and Ports
 A module definition always begins with the keyword
module.
➢ The module name,
➢ port list,
➢ port declarations, and
➢ optional parameters must come first in a module
definition.
 The five components within a module are –
variable declarations, dataflow statements, instantiation
of lower modules, behavioral blocks, and tasks or
functions.
 These components can be in any order and at any place in
the module definition.
 The endmodule statement must always come last in a
module definition.
 All components except module, module name, and
endmodule are optional and can be mixed and matched as
per design needs.

This example illustrates the
different components of a module
module SR-latch (Q, Qbar, Sbar, Rbar);
output Q, Qbar;
//Port declarations
input Sbar, Rbar;
// Instantiate lower-level modules
nand nl (Q, Sbar, Qbar) ;
nand n2 ( Qbar , Rbar , Q) ;
endmodule

moduleTop;
wire q, qbar;
reg set, reset;
// Instantiate lower-level modules
// In this case, instantiate SR-latch
// Feed inverted set and reset signals to the SR latch
SR-latch ml(q, qbar, -set, -reset);
// Behavioral block, initial
initial
begin
$monitor($time, " set = %b, reset= %b, q=
%bnU,set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
endmodule

Ports
 Ports provide the interface by which a
module can communicate with
environment.
 For example, the input/output pins of an
IC chip are its ports.
 The environment can interact with the
module only through its ports.
 The internals of the module are not
visible to the environment.
 The internals of the module can be
changed without affecting the
environment as long as the interface is
not modified.
 Ports are also referred to as terminals.

Ports:
 module definition contains an optional list of
ports.
 If the module does not exchange any signals
with the environment, there are no ports in
the list.
Ex. Consider a 4-bit full adder that is instantiated
inside a top-level module Top.
module fulladd4 (sum, c-out, a, b, c-in);
//module with a list of ports
moduleTop; // No list of ports, top-level
module in simulation

Ports
 Notice that in the above figure, the module
Top is a top-level module.
 The module fulladd4 is instantiated below Top.
The module fulladd4 takes input on ports a, b,
and c-in and produces an output on ports sum
and c-out.
• Thus, module fulladd4 performs an addition
for its environment.
• The module Top is a top-level module in the
simulation and does not need to pass signals
to or receive signals from the environment.
Thus, it does not have a list of ports

Port Declaration
 All ports in the list of ports must be
declared in the module. Ports can be
declared as follows:
 Each port in the port list is defined as input, output,
or inout, based on the direction of the port signal.
Thus, for the example of the fulladd4 in Example.

module fulladd4(sum, c-out, a, b, c-in);
//Begin port declarations section
output [3 : 0] sum;
output c-cout;
input [3:0] a, b;
input c-in;
//End port declarations section
...
<module internals>
...
endmodule

1.Gate level Modeling- Gate types, Gate
delays
2.Data flow modeling- Continuous
Assignments, Delays expression, operators
& operands
3.Behavioral Modeling- Structured
Procedures, Procedural Assignments,Timing
Controls, Conditional statements, Multiway
Branching, Loops

1.Gate level Modeling
 At gate level, the circuit is described in
terms of gates (e.g., and, nand).
 Hardware design at this level is intuitive for a
user with a basic knowledge of digital logic
design because it is possible to see a one-to-
one correspondence between the logic
circuit diagram and theVerilog description.
 Hence, we chose to start with gate-level
modeling and move to higher levels of
abstraction in the succeeding lectures.

1.Gate level Modeling
 GateTypes
 A logic circuit can be designed by use of
logic gates.Verilog supports basic logic gates
as predefined primitives.
 These primitives are instantiated like
modules except that they are predefined in
Verilog and do not need a module definition.
 All logic circuits can be designed by using
basic gates.
 There are two classes of basic gates: and l or
gates and buf l not gates

And/Or Gates
 and/or gates have one scalar output and
multiple scalar inputs.
 The first terminal in the list of gate
terminals is an output and the other
terminals are inputs.
 The output of a gate is evaluated as soon
as one of the inputs changes.

Gates:
and or xor
nand nor xnor

Buf/Not Gates
 Buf / not gates have one scalar input and
one or more scalar outputs.
Two basic buf l not gate primitives are
provided inVerilog.

// basic gate instantiations.
buf bl(OUT1, IN);
not nl(OUT1, IN);
// More than two outputs
buf bl_2out(OUTl, OUT2, IN);
// gate instantiation without instance
name
not (OUT1, IN); // legal gate
instantiation

 These gates are used when a signal is to
be driven only when the control signal is
asserted. Such a situation is applicable
when multiple drivers drive the signal.

Example
wire OUT, IN1, IN2;
// basic gate instantiations.
and a1(OUT, IN1, IN2);
nand nal (OUT, IN1, IN2 ) ;
or orl(OUT, IN1, IN2);
nor nor1 (OUT, IN1, IN2 ) ;
xor xl (OUT, IN1, IN2 ) ;
xnor nxl (OUT, IN1, IN2 ) ;
// More than two inputs; 3 input nand gate
nand nal-3 inp (OUT, IN1, IN2, IN3 ) ;
// gate instantiation without instance name
and (OUT, IN1, IN2); // legal gate instantiation

References
 Verilog HDL A guide to digital design &
synthesis By Samir Palnitkar, Pearson
Second Edition
 Fundamental of digital logic with Verilog
By Stephen Brown, Zvonko Vranesic,
Tata McGraw Hill

VHDL- gate level modelling

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