MHW (1st Term) Session:2024-25
Name: Class: IX Section: Roll No:
Subject: Computer Science Teacher: Wardah Murtahin Billah Jasir Full Marks: 18 Date:23.10.2024
Obtained Marks: Parents Signature: Teachers Signature:
Chapter 3 3.1 Computer Architecture Submission Date: 27-10-2024, Sunday
Q1. One of the key features of von Neumann computer architecture is the use of buses. Three buses and
three descriptions are shown below. Draw a line to connect each bus to its correct description. [3]
Bus Description
this bus carries signals used
Address Bus to coordinate the computer’s
activities
this bi-directional bus is used to
Address Bus exchange data between
processor, memory and input/
output devices
this uni-directional bus carries
Address Bus signals relating to memory
addresses between processor
and memory
Q2. The computer processes instructions using the (FDE) cycle. Draw and annotate a diagram to show
the process of the fetch stage of the FDE cycle. [4]
Q3. The seven stages in a von Neumann fetch-execute cycle are shown in the table below. Put each stage
in the correct sequence by writing the numbers 1 to 7 in the right-hand column. The first one has been
done for you. [6]
Stage Sequence
number
the instruction is then copied from the memory location contained
in the MAR (memory address register) and is placed in the MDR
(memory data register)
the instruction is finally decoded and is then executed
the PC (program counter) contains the address of the next instruction 1
to be fetched
the entire instruction is then copied from the MDR (memory data
register) and placed in the CIR (current instruction register)
the address contained in the PC (program counter) is copied to the
MAR (memory address register) via the address bus
the address part of the instruction, if any, is placed in the MAR
(memory address register)
the value in the PC (program counter) is then incremented so that it
points to the next instruction to be fetched
Q4. A computer is designed using the Von Neumann model for a computer system.
The computer has a central processing unit (CPU).
(a) Data is fetched from primary storage into the CPU to be processed.
(i) State the name of the primary storage from where data is fetched.
................................................................................................................... [1]
(ii) The CPU performs a cycle to process data. Fetch is the first stage in this cycle.
State the names of the second and third stages in the cycle.
Second stage ........................................................................................................
Third stage ............................................................................................................ [2]
(iii) Identify two components within the CPU that are used in the fetch stage of the cycle.
Component 1 ..................................................................................................
Component 2 ................................................................................................... [2]
Good Luck.
