Unit 1 basic structure of computers

UNIT 1 - Basic Structure
of Computers

Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

Information Handled by a
Computer
 Instructions/machine instructions
 Govern the transfer of information within a computer as
well as between the computer and its I/O devices
 Specify the arithmetic and logic operations to be
performed
 Program
 Data
 Used as operands by the instructions
 Source program
 Encoded in binary code – 0 and 1

Memory Unit
 Store programs and data
 Two classes of storage
 Primary storage
 Fast
 Programs must be stored in memory while they are being executed
 Large number of semiconductor storage cells
 Processed in words
 Address
 RAM and memory access time
 Memory hierarchy – cache, main memory
 Secondary storage – larger and cheaper

Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in
ALU of the processor.
 Load the operands into memory – bring them
to the processor – perform operation in ALU –
store the result back to memory or retain in
the processor.
 Registers
 Fast control of ALU

Control Unit
 All computer operations are controlled by the control
unit.
 The timing signals that govern the I/O transfers are
also generated by the control unit.
 Control unit is usually distributed throughout the
machine instead of standing alone.
 Operations of a computer:
 Accept information in the form of programs and data through an
input unit and store it in the memory
 Fetch the information stored in the memory, under program control,
into an ALU, where the information is processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control unit

The processor : Data Path and
Control

Data
PC Address Register #
Register A
Instructions Bank L Address
U
Register #
Instruction Data Memory
Memory
Register #
Data

Two types of functional units:
elements that operate on data values (combinational)
 elements that contain state (state elements)

Five Execution Steps
Step name Action for R-type Action for Memory- Action for Action for
instructions reference Instructions branches jumps

Instruction fetch IR = MEM[PC]
PC = PC + 4

Instruction decode/ register A = Reg[IR[25-21]]
fetch B = Reg[IR[20-16]]
ALUOut = PC + (sign extend (IR[15-0])<<2)

Execution, address ALUOut = A op B ALUOut = A+sign IF(A==B) Then PC=PC[31-28
computation, branch/jump extend(IR[15-0]) PC=ALUOut ]||
completion (IR[25-0]<<2)

Memory access or R-type Reg[IR[15-11]] = Load:MDR =Mem[ALUOut]
completion ALUOut or
Store:Mem[ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] =
MDR

Basic Operational
Concepts

Review
 Activity in a computer is governed by instructions.
 To perform a task, an appropriate program
consisting of a list of instructions is stored in the
memory.
 Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
 Data to be used as operands are also stored in the
memory.

A Typical Instruction
 Add LOCA, R0
 Add the operand at memory location LOCA to the
operand in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the
processor – the operand at LOCA is fetched and
added to the contents of R0 – the resulting sum is
stored in register R0.

Separate Memory Access and
ALU Operation
 Load LOCA, R1
 Add R1, R0
 Whose contents will be overwritten?

Connection Between the
Processor and the Memory
Memory

MAR MDR
Control

PC R0

R1
Processor
IR

ALU
Rn 1

n general purpose
registers

Figure 1.2. Connections between the processor and the memory.

Registers
 Instruction register (IR)
 Program counter (PC)
 General-purpose register (R0 – Rn-1)
 Memory address register (MAR)
 Memory data register (MDR)

Typical Operating Steps
 Programs reside in the memory through input
devices
 PC is set to point to the first instruction
 The contents of PC are transferred to MAR
 A Read signal is sent to the memory
 The first instruction is read out and loaded
into MDR
 The contents of MDR are transferred to IR
 Decode and execute the instruction

Typical Operating Steps
(Cont’)
 Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)
 Perform operation in ALU
 Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
 During the execution, PC is
incremented to the next instruction

Interrupt
 Normal execution of programs may be preempted if
some device requires urgent servicing.
 The normal execution of the current program must
be interrupted – the device raises an interrupt
signal.
 Interrupt-service routine
 Current system information backup and restore (PC,
general-purpose registers, control information,
specific information)

Bus Structures
 There are many ways to connect different
parts inside a computer together.
 A group of lines that serves as a connecting
path for several devices is called a bus.
 Address/data/control

Bus Structure
 Single-bus

Input Output Memory Processor

Figure 1.3. Singlebus structure.

Speed Issue
 Different devices have different
transfer/operate speed.
 If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
 How to solve this?
 A common approach – use buffers.

Performance
 The most important measure of a computer is
how quickly it can execute programs.
 Three factors affect performance:
 Hardware design
 Instruction set
 Compiler

Performance
 Processor time to execute a program depends on the hardware
involved in the execution of individual machine instructions.

Main Cache
memory memory Processor

Bus

Figure 1.5. The processor cache.

Performance
 The processor and a relatively small cache
memory can be fabricated on a single
integrated circuit chip.
 Speed
 Cost
 Memory management

Processor Clock
 Clock, clock cycle, and clock rate
 The execution of each instruction is divided
into several steps, each of which completes
in one clock cycle.
 Hertz – cycles per second

Basic Performance Equation
 T – processor time required to execute a program that has been
prepared in high-level language
 N – number of actual machine language instructions needed to
complete the execution (note: loop)
 S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
 R – clock rate
 Note: these are not independent to each other

N×S
T=
R
How to improve T?

Pipeline and Superscalar
Operation
 Instructions are not necessarily executed one after
another.
 The value of S doesn’t have to be the number of
clock cycles to execute one instruction.
 Pipelining – overlapping the execution of successive
instructions.
 Add R1, R2, R3
 Superscalar operation – multiple instruction
pipelines are implemented in the processor.
 Goal – reduce S (could become <1!)

Clock Rate
 Increase clock rate
 Improve the integrated-circuit (IC) technology to make
the circuits faster
 Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps
needed)
 Increases in R that are entirely caused by
improvements in IC technology affect all
aspects of the processor’s operation equally
except the time to access the main memory.

CISC and RISC
 Tradeoff between N and S
 A key consideration is the use of pipelining
 S is close to 1 even though the number of basic steps
per instruction may be considerably larger
 It is much easier to implement efficient pipelining in
processor with simple instruction sets
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)

Compiler
 A compiler translates a high-level language program
into a sequence of machine instructions.
 To reduce N, we need a suitable machine instruction
set and a compiler that makes good use of it.
 Goal – reduce N×S
 A compiler may not be designed for a specific
processor; however, a high-quality compiler is
usually designed for, and with, a specific processor.

Performance Measurement
 T is difficult to compute.
 Measure computer performance using benchmark programs.
 System Performance Evaluation Corporation (SPEC) selects and
publishes representative application programs for different application
domains, together with test results for many commercially available
computers.
 Compile and run (no simulation)
 Reference computer

Running time on the reference computer
SPEC rating =
Running time on the computer under test
n 1
SPEC rating = (∏SPECi ) n

i =1

Machine Instructions
and Programs

Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Number representation and addition/subtraction in
the 2’s-complement system.
 Addressing methods for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.

Memory Locations,
Addresses, and
Operations

Memory Location, Addresses,
and Operation
n bits
first word
 Memory consists
second word
of many millions of
storage cells,
•
each of which can •
•
store 1 bit.
 Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure 2.5. Memory words.

and Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII
character character character character

(b) Four characters

and Operation
 To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240

and Operation
 It is impractical to assign distinct addresses
to individual bit locations in the memory.
 The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…

Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 4 2 4 2 3 2 2 2 1 2 4 2 1 2 2 2 3 2 4

(a) Bigendian assignment (b) Littleendian assignment

Figure 2.7. Byte and word addressing.

and Operation
 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and character
strings

Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used

Instruction and
Instruction Sequencing

“Must-Perform” Operations
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

Register Transfer Notation
 Identify a location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
 Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
 Register Transfer Notation (RTN)

Assembly Language Notation
 Represent machine instructions and
programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]

CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register bookkeeping
 Stack
 Operands and result are always in the stack

Instruction Formats
 Three-Address Instructions
 ADD R1, R2, R3 R1 ← R2 + R3
 Two-Address Instructions
 ADD R1, R2 R1 ← R1 + R2
 One-Address Instructions
 ADD M AC ← AC + M[AR]
 Zero-Address Instructions
 ADD TOS ← TOS + (TOS – 1)
 RISC Instructions
 Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) ∗ (C+D)
 Three-Address
l ADD R1, A, B ; R1 ← M[A] + M[B]
l ADD R2, C, D ; R2 ← M[C] + M[D]
l MUL X, R1, R2 ; M[X] ← R1 ∗ R2

Instruction Formats
 Two-Address
l MOV R1, A ; R1 ← M[A]
l ADD R1, B ; R1 ← R1 + M[B]
l MOV R2, C ; R2 ← M[C]
l ADD R2, D ; R2 ← R2 + M[D]
l MUL R1, R2 ; R1 ← R1 ∗ R2
l MOV X, R1 ; M[X] ← R1

Instruction Formats
 One-Address
l LOAD A ; AC ← M[A]
l ADD B ; AC ← AC + M[B]
l STORET ; M[T] ← AC
l LOAD C ; AC ← M[C]
l ADD D ; AC ← AC + M[D]
l MUL T ; AC ← AC ∗ M[T]
l STOREX ; M[X] ← AC

Instruction Formats
 Zero-Address
l PUSH A ; TOS ← A
l PUSH B ; TOS ← B
l ADD ; TOS ← (A + B)
l PUSH C ; TOS ← C
l PUSH D ; TOS ← D
l ADD ; TOS ← (C + D)
l MUL ; TOS ←
(C+D)∗(A+B)
l POP X ; M[X] ← TOS

Instruction Formats
 RISC
l LOAD R1, A ; R1 ← M[A]
l LOAD R2, B ; R2 ← M[B]
l LOAD R3, C ; R3 ← M[C]
l LOAD R4, D ; R4 ← M[D]
l ADD R1, R1, R2 ; R1 ← R1 + R2
l ADD R3, R3, R4 ; R3 ← R3 + R4
l MUL R1, R1, R3 ; R1 ← R1 ∗ R3
l STOREX, R1 ; M[X] ← R1

Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller (e.g. 32
registers need 5 bits)
 Potential speedup
 Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

Instruction Execution and
Straight-Line Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i + 4
3instruction
program
- One memory operand
Add B,R0
segment per instruction
i + 8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

Figure 2.8. A program for C ← [Α] + [Β].

i Move NUM1,R0
i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
i + 4n 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure 2.9. A straightline program for adding n numbers.

Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch
•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUMn

Condition Codes
 Condition code flags
 Condition code register / status register
 N (negative)
 Z (zero)
 V (overflow)
 C (carry)
 Different instructions affect different flags

Conditional Branch
Instructions
 Example: A: 11110000
 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0

Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check

Generating Memory Addresses
 How to specify the address of branch target?
 Can we give the memory operand address
directly in a single Add instruction in the
loop?
 Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

Addressing Modes

Opcode Mode ...
 Implied
 AC is implied in “ADD M[AR]” in “One-Address”
instr.
 TOS is implied in “ADD” in “Zero-Address” instr.
 Immediate
 The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
 Register
 Indicate which register holds the operand

Addressing Modes
 Register Indirect
 Indicate the register that holds the number of the
register that holds the operand R1
MOV R1, (R2)
R2 = 3
 Autoincrement / Autodecrement
 Access & update in 1 instr. R3 = 5
 Direct Address
 Use the given address to access a memory
location

Addressing Modes
 Indirect Address
 Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A

Addressing Modes

 Relative Address
0
 EA = PC + Relative Addr 1
PC = 2 2

+

100
AR = 100
101
102 1 1 0 A
Could be Positive 103
or Negative 104
(2’s Complement)

Addressing Modes
 Indexed
 EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive
or Negative 102 1 1 0 A
(2’s Complement) 103
104

Addressing Modes
 Base Register
 EA = Base Register + Relative Addr

Could be Positive AR = 2
or Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points 103 0 1 0 7
to the beginning 104 0 0 5 9
of an array

Addressing Modes
Name Assembler syntax Addressing function
 The different
ways in which Immediate #Value Op erand = Value
the location of
an operand is Register Ri EA = Ri
specified in Absolute (Direct) LOC EA = LOC
an instruction
are referred to Indirect (Ri ) EA = [Ri ]
as addressing (LOC) EA = [LOC]
modes.
Index X(R i) EA = [Ri ] + X

Basewith index (Ri ,Rj) EA = [Ri ] + [Rj]
Basewith index X(R i,Rj) EA = [Ri ] + [Rj] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincrement (Ri )+ EA = [Ri ] ;
Increment Ri

Autodecrement − (Ri ) Decrement Ri ;
EA = [Ri]

Indexing and Arrays
 Index mode – the effective address of the operand
is generated by adding a constant value to the
contents of a register.
 Index register
 X(Ri): EA = X + [Ri]
 The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
 If X is shorter than a word, sign-extension is
needed.

Indexing and Arrays
 In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
 Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]

Relative Addressing
 Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it as an
offset from the current value of PC.
 Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.

Additional Modes
 Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
 (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
 Autodecrement mode: -(Ri) – decrement first
Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.

Types of Instructions
 Data Transfer Instructions
Name Mnemonic Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1

Data Manipulation Instructions
 Arithmetic Name Mnemonic
Increment INC
 Logical & Bit Manipulation Decrement DEC
Add ADD
 Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Negate NEG
Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement
COMC Rotate left ROL
carry Rotate right through
Enable interrupt EI RORC
Disable interrupt DI carry
Rotate left through carry ROLC

Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000

Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition
BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
Branch if no
BNV V=0
overflow

Basic Input/Output
Operations

I/O
 The data on which the instructions operate
are not necessarily already stored in memory.
 Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
 I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.

Program-Controlled I/O
Example
 Read in character input from a keyboard and
produce character output on a display
screen.
 Rate of data transfer (keyboard, display, processor)
 Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
 A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.

Example
Bus

Processor
DATAIN DATAOUT

SIN SOUT
- Registers
- Flags Keyboard Display
- Device interface

Figure 2.19 Bus connection for processor, keyboard, and display.

Example
 Machine instructions that can check the state
of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0
Output from R1 to DATAOUT

Example
 Memory-Mapped I/O – some memory
address values are used to refer to peripheral
device buffer registers. No special
instructions are needed. Also use device
status registers.

READWAIT Testbit #3, INSTATUS
Branch=0 READWAIT
MoveByte DATAIN, R1

Example
 Assumption – the initial state of SIN is 0 and the
initial state of SOUT is 1.
 Any drawback of this mechanism in terms of
efficiency?
 Two wait loopsprocessor execution time is wasted
 Alternate solution?
 Interrupt

Stack Organization

Current
Top of Stack
 LIFO TOS 0
Last In First Out 1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack

Stack Organization

Current 1 6 9 0
Top of Stack
 PUSH TOS 0
SP ← SP – 1 1
M[SP] ← DR 2
3
If (SP = 0) then (FULL ← 1) 4
EMPTY ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
9 0 0 2 5
Stack

Stack Organization
Current
Top of Stack
 POP TOS 0
DR ← M[SP] 1
SP ← SP + 1 2
3
If (SP = 11) then (EMPTY ← 1) 4
FULL ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
9 0 0 2 5
Stack

Stack Organization
 Memory Stack
 PUSH PC 0
1
SP ← SP – 1 2
M[SP] ← DR
 POP AR 100
101
DR ← M[SP]
102
SP ← SP + 1
200
SP 201
202

Unit 1 basic structure of computers

More Related Content

What's hot

Viewers also liked

Similar to Unit 1 basic structure of computers

More from chidabdu

Recently uploaded

In this document

Unit 1 basic structure of computers