Download to read offline
Uploaded byDaniel Roggen
W10: Interrupts
The document discusses digital systems and microprocessor design, focusing on interrupts as a means to change program flow upon hardware events. It explains the concepts of polling versus external interrupts for managing input pins and emphasizes the speed advantage of interrupts in multitasking environments. Additionally, it includes details about handling interrupts, the interrupt vector table, and the distinction between external and internal interrupts.
More Related Content
![[DCG 25] Александр Большев - Never Trust Your Inputs or How To Fool an ADC](https://cdn.slidesharecdn.com/ss_thumbnails/presentationdefconrussia-160406215741-thumbnail.jpg?width=600ounds&width=560&fit=bounds)
W10: Interrupts
- 1. 1 Digital Systems andMicroprocessor Design (H7068) Daniel Roggen d.roggen@sussex.ac.uk 10.2. Interrupts
- 2. 2 Content • Summary: discontinuitiesin program flow – Jumps – Reset • Interrupts: changing the program flow upon hardware event • External interrupts • Internal interrupts
- 3. 3 Program flow PC AdrInst -> 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ...
- 4. 4 Program flow PC AdrInst 00 mov ra,42 -> 02 mov rb,3 04 add ra,rb 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ...
- 5. 5 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 -> 04 add ra,rb 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ...
- 6. 6 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb -> 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ... Under “normal” circumstances PC is incremented to point to the next instruction (after each instruction / clock cycle, depending on the implementation) In the Educational Processor PC is incremented by 1 in the fetchh and fetchl cycles
- 7. 7 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 -> 08 ja 0Ch 0A jmp 04 0C ... 0E ... PC is not always incremented to point to the next instruction: • Conditional jumps • Unconditional jumps Here the conditional jump is not taken
- 8. 8 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 08 ja 0Ch -> 0A jmp 04 0C ... 0E ... This unconditional jump is taken PC is not always incremented to point to the next instruction: • Conditional jumps • Unconditional jumps
- 9. 9 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 -> 04 add ra,rb 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ... Habitual program flow continues jm p
- 10. 10 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb -> 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ...
- 11. 11 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 -> 08 ja 0Ch 0A jmp 04 0C ... 0E ... clk rst Reset creates a discontinuity in the program flow: PC set to 0 Really: more than a discontinuity as all registers are cleared – but fundamentally it is a discontinuity
- 12. 12 Program flow PC AdrInst 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 08 ja 0Ch -> 0A jmp 04 0C ... 0E ... clk rst Let’s reset the processor!
- 13. 13 Program flow PC AdrInst -> 00 mov ra,42 02 mov rb,3 04 add ra,rb 06 cmp ra,70 08 ja 0Ch 0A jmp 04 0C ... 0E ... clk rst Processor after reset: PC=0 rst
- 14. 14 From reset tointerrupts • Reset is a an external signal that changes the flow of execution • Interrupts are another mechanism by which an external signal can change the execution flow • Interrupts exist on all commercial processors and microcontrollers! • Note: there are no interrupts in the educational processor... clk rst
- 15. 15 Motivation for interrupts •Let’s say a program must wait until a pin goes high on the external interface…. – for example to count how often a pin is toggled – Or to implement a communication protocol in software (e.g. I2C, SPI, etc) • How to implement this in a program? clk rst Ext interface
- 16. 16 Polling • Implementation bypolling: continuously reading the pin to detect changes mov ra,0 // number of toggles testbit: in rb // read ext input and rb,1 // check bit 0 cmp rb,1 // bit 0 set? jne testbit // add ra,1 // increment counter // instead of increment we // could do more complex stuff waitclr: // now wait until clear in rb and rb,1 cmp rb,0 // bit clear? jne waitclr // no, loop until clear jmp testbit // yes, go back to test bit set
- 17. 17 Polling • Latency? – 7instructions to react to rising edge (worst case) – 8 instructions to react to falling edge (worst case) mov ra,0 // number of toggles testbit: in rb // read ext input and rb,1 // check bit 0 cmp rb,1 // bit 0 set? jne testbit // add ra,1 // increment counter // instead of increment we // could do more complex stuff waitclr: // now wait until clear in rb and rb,1 cmp rb,0 // bit clear? jne waitclr // no, loop until clear jmp testbit // yes, go back to test bit set
- 18. 18 Polling • Latency? – 7instructions to react to rising edge – 8 instructions to react to falling edge • Total: 15*3=45 processor clock cycles to detect one cycle on the external input! • If the external signal toggles with a period smaller than 45 clock cycles then the processor cannot count the number of toggles! 45clk Ext input:
- 19. 19 Polling • Polling isusually a very slow solution (compared to a hardware approach) to the problem of detecting changes on input pins – 1/45th speed of processor in this example! (100MHz->2MHz) – (although some specific use cases are suitable for polling!) • During polling the processor cannot do anything else! • Not suitable for multitasking
- 20. 20 Solution 1: hardware •Hardware counter (outside of processor) • Hardware interface: see previous lectures – There are hardware interfaces dedicated to "count" events in many microcontrollers! • (however that's not the point of this lecture)
- 21. 21 Solution 2: externalinterrupt • An external interrupt is a condition on a external pin that triggers an interruption of the normal program flow • Several conditions can trigger ints (usually configurable): – Rising edge – Falling edge – Any edge – Level-triggered Ext interface clk rst pin that generates an interrupt
- 22. 22 External interrupts • Externalcondition interrupts program flow • PC set to jump to an interrupt vector • Interrupt vector: piece of code that will handle the interrupt (do something in reaction to it) • There can be multiple interrupts! – E.g. one per pin FLASH RAM Int vect 1 Int vect 2
- 23. 23 External interrupts • Thefollowing happens during an interrupt: • The processor keeps a return address: – Address of PC before the interrupt • PC set to the interrupt vector (i.e. jump to IV) • The processor executes the instructions in the interrupt vector • Interrupt return instruction (RETI) – Indicates the end of the interrupt routine – The processor returns to the PC value before the interrupt (return address) FLASH RAM Int vect 1 Int vect 2
- 24. 24 Interrupt vector table •Processor jumps to a fixed location! (interrupt vector) – Typically at the start or end of memory • Interrupt vector table (IVT): with multiple interrupts, all interrupt vectors follow each other • Each entry is one instruction wide • Reset can sometimes be seen as an entry in the IVT Adr What ----- ------ 00-01 First instruction on reset 02-03 Int0 (First instruction of Int0) 04-05 Int1 (First instruction of Int1) ... 0A-0B First "normal" program instruction
- 25. 25 Interrupt vector table •The IVT holds only one instruction per interrupt! – How to have an interrupt routine of more than one instruction?? • A jump (one instruction) is stored in the IVT • This allows to program the location of interrupt routine – The programmer can decide where to place the interrupt routine! • The program continues until the RETI instruction Adr What ----- ------ 00-01 First instruction on reset 02-03 Int0 (First instruction of Int0) 04-05 Int1 (First instruction of Int1) ... 0A-0B First "normal" program instruction
- 26. 26 IVT example Adr What ----------- 00-01 jmp 20 02-03 jmp 80 04-05 jmp A0 20-21 First program instruction ..... 78-79 Last possible program instruction 80-81 First instruction for Int0 ..... A0-A1 First instruction for Int1 .....
- 27. 27 Using interrupt tocount toggles • Assumption: int0 is called on rising edge of a pin Adr 00 jmp 10h 02 jmp 20h 10 mov ra,0h // number of toggles 12 ... // do 14 ... // something 16 ... // continuously 18 jmp 12h // here 20 add ra,1h // increment counter 22 reti // interrupt return
- 28. 28 Using interrupt tocount toggles • Latency? – 1 instruction to go to interrupt vector – 1 instruction to return from interrupt vector Adr 00 jmp 10h 02 jmp 20h 10 mov ra,0h // number of toggles 12 ... // do 14 ... // something 16 ... // continuously 18 jmp 12h // here 20 add ra,1h // increment counter 22 reti // interrupt return
- 29. 29 External interrupts • Externalinterrupts are a very fast approach to react to external events! – 2 instruction latency instead of 15 -> 7.5x speedup! • Interrupts permit the processor to execute a main task and occasionally process "urgent" events • Processors have an "interrupt pin" that can be used by peripherals (I/O interfaces) to trigger interrupts – Often used in microcontrollers – E.g. Interrupt once byte is sent over I2C • Commonly used for: – communication – storage devices – user interaction – sensor sampling • Foundation of multitasking
- 30. 30 comp_ip: entity work.dffregeneric map(N=>N) port map(clk=>clk,rst=>rst,en=>'1',d=>ipnext,q=>ip); ipnext <= ip+1 when fetch='1' else ip when jump='0' else jumpip; • Educational processor has no interrupts! – ip incremented in the fetchh and fetchl cycles – In exec cycle ip is unchanged if there is no jump, – or ip is set to the jump address if there is jump • unconditional jump • conditional jump with a valid jump condition Possible Implementation
- 31. 31 comp_ip: entity work.dffregeneric map(N=>N) port map(clk=>clk,rst=>rst,en=>'1',d=>ipnext,q=>ip); ipnext <= ip+1 when fetch='1' else ip when jump='0' and int ='0' else iv when int='1' else jumpip; • Adding an interrupt: – Implemented in the same way as a jump – int indicates an interrupt: e.g. can be level of a signal of the external input interface – iv is the address of the interrupt vector (e.g. "02" in the previous example) Possible Implementation
- 32. 32 • Additionally (notshown here): – Keep the return address (PC before modification stored in a register or memory – Implement the RETI instruction (e.g. using a spare opcode) Possible Implementation
- 33. 33 Internal interrupts • Externalinterrupts react to external events (on pins) • Internal interrupts react to processor events • Common processor events: – Division by zero / invalid math operation – Invalid opcode – Data alignment check – etc • For example, "invalid opcode" could be used to emulate new opcodes on an older processor!
- 34. 34 Summary • Interrupts changethe control flow until a RETI instruction • Multiple interrupts can placed in programmer-defined memory location using the interrupt vector table • External interrupts allow very fast reaction to external events while allowing multitasking! • External interrupts include pin change interrupts and peripheral interrupts • Processors have internal interrupts to indicate issues